1. Field of the Invention
The present invention relates to a printed board and a semiconductor integrated circuit and, more particularly, to, e.g., an IC such as an ASIC having a plurality of power supply and GND terminals and a printed board with an IC mounted.
2. Description of the Related Art
In recent semiconductor integrated circuits (to be referred to as ICs hereinafter), the packaging density is increasing along with the progress of microfabrication technology, and the scale of circuits mounted in ICs is dramatically becoming large. Especially in an IC chip structure roughly divided into an internal core circuit and an I/O buffer part, the density in the internal core circuit rises. As a result, the number of switching elements such as CMOS formed in the internal core circuit increases, and the operation speed becomes higher year after year.
Since an enormous number of switching elements formed in the internal core circuit repeatedly turn on/off simultaneously in a clock cycle to operate the IC, an instantaneous carrying current is generated at the same timing. The instantaneous carrying current drops the voltage by an impedance that is parasitic to the path of the current flowing to wiring lines inside the IC and print patterns outside the IC. The periodical potential variation at a high frequency acts as a noise source. The noise is propagated through the printed board with the IC and even the entire device having the printed board.
The internal arrangement of an IC is roughly divided into an internal core circuit part and an I/O buffer part serving as an interface to an external device, as described above. In the conventional IC, the power supply wiring line of the internal core circuit part and the power supply wiring line and GND wiring line of the I/O buffer part are formed as a common wiring line in the IC.
When the power supply and GND wiring lines of the internal core circuit part and I/O buffer part are commonly formed in the IC, a high-frequency potential variation generated in the power supply and GND wiring lines of the internal core circuit part is propagated to those of the I/O buffer part. The high-frequency potential variation propagated to the power supply and GND wiring lines is output because connection to the power supply wiring line occurs when the signal output terminal of the I/O buffer part is at a high level (H) while connection to the GND wiring line occurs at a low level (L).
In addition, the high-frequency potential variation is propagated to the signal output terminal via a parasitic capacitance between the signal output terminal and the power supply wiring line of the I/O buffer part and a parasitic capacitance between the signal output terminal and the GND wiring line of the I/O buffer part. Even a parasitic capacitance with a high frequency drops the impedance so that the noise is propagated. For example, when the parasitic capacitance is 10 pF and the frequency of the noise component is 200 MHz, the impedance of the parasitic capacitance is about 80Ω. That is, the parasitic capacitance causes noise propagation to the signal output terminal although its magnitude changes depending on the magnitude of the parasitic capacitance in the I/O buffer part and the noise frequency.
The high-frequency potential variation propagated to the signal output terminal is propagated to the printed board, cable, and metal case and finally increases the radiant noise level from the device.
The signal input terminal of the I/O buffer part high-frequency-couples to the power supply wiring line and, more particularly, to the GND wiring line in the IC chip via the parasitic capacitance. For this reason, the high-frequency potential variation generated in the power supply and GND wiring lines by the instantaneous carrying current in the internal core circuit is propagated to the printed board via the terminal. This increases the radiant noise level from the device, as in the signal output terminal.
Under these circumstances, many techniques of isolating wiring lines in an IC have been proposed so far, mainly aiming at suppressing the above-described noise interference in the IC, as will be described below.
Japanese Patent Laid-Open No. 61-119071 (patent reference 1) discloses a wiring structure in an IC, in which at least one of the power supply of at least one specific circuit and a reference potential wiring line is electrically disconnected and insulated from the power supply of another circuit formed on the same chip as the specific circuit and/or the reference potential wiring line. Even when a large current flows to the specific circuit and generates noise, the noise pulse is not transmitted to other circuits. This prevents any circuit operation error by the noise.
Japanese Patent Laid-Open No. 5-67682 (patent reference 2) discloses a wiring structure in an IC, in which the power supply layer and ground layer of a semiconductor chip are isolated from a signal wiring line layer. In addition, each of the power supply layer and ground layer separately has an input buffer, output buffer, and internal logic circuit. This easily provides a measure against the influence of switching noise upon simultaneous operation of output buffers.
Japanese Patent Laid-Open No. 6-37258 (patent reference 3) discloses an IC having a double-layer structure which incorporates a circuit formed by connecting elements provided on a predetermined substrate by using wiring lines provided in a plurality of wiring layers. In particular, the IC includes a plurality of wiring lines which are formed in the plurality of wiring layers and have a layout pattern to isolate a circuit part serving as a noise source from a circuit part for reducing noise, and contacts for connecting the plurality of wiring lines. The IC further comprises a constant potential wiring line to connect the plurality of wiring lines connected to each other to a constant potential part. This suppresses a signal from a circuit part in the IC from being induced to another circuit part in the IC as noise.
Japanese Patent Laid-Open No. 6-112320 (patent reference 4) is related to an IC having first power supply and GND wiring lines and second power supply and GND wiring lines. According to patent reference 4, the first power supply and GND wiring lines are isolated from the second power supply and GND wiring lines. The first power supply and GND wiring lines connect to output buffer circuits which operate simultaneously. The second power supply and GND wiring lines connect to input/output buffer circuits other than the output buffer circuits. That is, patent reference 4 provides an effect of largely increasing the number of simultaneously operated output buffer circuits by isolating the power supply and GND wiring lines of the output and input buffer circuits which operate simultaneously.
Japanese Patent Laid-Open No. 7-74259 (patent reference 5) is related to a semiconductor memory having a plurality of output terminals. As a characteristic feature of patent reference 5, power supply and GND wiring lines connected to output transistors arranged for the output terminals are isolated from adjacent wiring lines. This can reduce the influence from peripheral circuits and the influence from other adjacent output circuits. Especially, the wiring width can be reduced by connecting some of power supply wiring lines or (GND wiring lines) arrayed in parallel, thus providing an effect of suppressing any increase in the area.
As the operation speed of an IC increases, the amount of noise generated by a variation in the GND or power supply voltage during the operation increases in the external output terminal. When the working voltage of the IC drops, the noise margin also decreases. Accordingly, an operation error caused by noise during use poses a serious problem. To solve this problem, Japanese Patent Laid-Open No. 5-291511 (patent reference 6) proposes an IC in which peripheral power supply and GND wiring lines for an external output terminal or external input/output terminal are separated, on the pattern in the IC, from internal circuit power supply and GND wiring lines which supply a power supply voltage to an internal circuit. This prevents noise generated in the former wiring lines from influencing the internal circuit connected to the latter wiring lines.
Japanese Patent Laid-Open No. 9-8233 (patent reference 7) is related to an IC having, as an internal circuit, a circuit which generates/outputs a periodic pulse signal and a circuit which operates on the basis of the periodic pulse signal. As a characteristic feature of the IC, each of the internal circuits and an output circuit including a load means for pulling up or down an input terminal and a driving means for driving an output terminal separately comprises power supply and GND wiring lines and power supply and GND terminals. Circuits which often process the periodic pulse signal are grouped as the internal circuits and separated from the power supply system of the output circuit including the load means for pulling up or down the input terminal and the driving means for driving the output terminal. Harmonic noise generated in the internal circuits does not radiate not only from the output terminal but also from the input terminal that is pulled up or down. Patent reference 7 can limit the noise radiation source to only the power supply system of the internal circuits and reduce the periodic spectral harmonics electromagnetically radiated from the IC.
The power supply wiring line and GND wiring line isolated from each other in the IC are high-frequency-isolated by the inductance component parasitic to the wiring part in the semiconductor chip and the parasitic inductance component of the bonding wires that connect the semiconductor chip to the lead frame. Hence, it is possible to prevent any operation errors and noise propagation independently of the pattern wiring on the printed board.
As described above, many techniques of isolating the power supply and GND wiring lines of each functional block from those of other functional blocks in an IC have been disclosed to prevent various kinds of noise interference in the IC.
Even for a printed board with a plurality of ICs, various proposals have been made to solve the problems concerned with noise, such as radiant noise and operation errors, by isolating the power supply wiring lines or GND wiring lines of the ICs or separating a high frequency by using, e.g., an inductance element.
For example, each of Japanese Patent Laid-Open No. 5-13909 (patent reference 8), Japanese Patent Laid-Open No. 10-41629 (patent reference 9), Japanese Patent Laid-Open No. 10-223997 (patent reference 10), Japanese Patent Laid-Open No. 11-233951 (patent reference 11), Japanese Patent Laid-Open No. 2001-274558 (patent reference 12), Japanese Patent Laid-Open No. 2003-69169 (patent reference 13), Japanese Patent Laid-Open No. 2003-133747 (patent reference 14), and Japanese Patent Laid-Open No. 2003-282781 (patent reference 15) discloses a printed board in which the wiring line of the external power supply terminal or GND terminal of an IC is physically pattern-isolated or isolated by using an inductance element from those of other ICs mounted on the printed board.
Patent reference 15 discloses a multi-layered circuit board with an IC such as an ASIC having a plurality of power supply terminals and GND terminals. Patent reference 15 discloses the following arrangement to provide a circuit board capable of reducing EMI noise radiated from the circuit board while suppressing the number of bypass capacitors. A main power supply plane and a sub power supply plane which is formed into an island shape and has a clearance to ensure electrical disconnection from the main power supply plane are provided in a first layer. A first power supply pattern which is formed in a layer different from the first layer and connected to a bypass capacitor connects the main power supply plane to the sub power supply plane. Power supply to at least some power supply terminals of the IC is done via a second power supply pattern which connect to the sub power supply plane without intervening a bypass capacitor.
As described above, the packaging density of an internal core circuit is increasing every day along with the progress of microfabrication technology. The number of switching elements such as CMOS formed in the internal core circuit is further increasing, and its operation speed is constantly becoming higher.
The arrangements proposed by patent references 1 to 7, which isolate power supply and GND wiring lines in an IC to prevent noise generated in the internal core circuit of the IC from being propagated to other block circuits, do not suffice. In other words, improvements from two aspects, i.e., a measure for the internal arrangement of an IC and an improved pattern wiring method for a printed board are necessary.
Patent references 8 to 14 disclose a printed board with a plurality of ICs in which the power supply patterns or GND patterns of the ICs are isolated by wiring or by using inductance elements. These arrangements can prevent a high-frequency potential variation that occurs in the power supply terminal or GND terminal of each of the ICs separately mounted on the printed board from being propagated to the power supply terminals or GND terminals of other ICs.
However, in an IC such as an ASIC having a plurality of functional blocks in one package, each functional block has a power supply terminal and a GND terminal. The power supply terminals or GND terminals of a single IC are connected by one wiring line on the printed board. For this reason, a potential variation caused by a high-frequency current generated in the internal core circuit is propagated to the power supply terminals or GND terminals of all I/O buffers via the pattern on the printed board. Hence, the high-frequency potential variation is propagated to input/output signal lines from all I/O buffers.
As a result, the high-frequency potential variation propagated to the signal input terminals and signal output terminals is propagated to the printed board, cable, and metal case as high-frequency noise. The cable serves as an antenna to radiate the propagated noise. The metal case may serve as a noise radiant antenna depending on its shape. For example, a metal case formed by juxtaposing flat metal sheets at very short intervals or a plurality of cases having a long gap at their joints, serve as antennas.
In a device formed by wholly enclosing the printed board and the cable by a box-shaped metal case, noise propagated to the cable is finally shielded by the BOX-shaped metal case. Hence, the radiant noise level from the device is low. In the BOX-shaped metal case enclosing the device, the metal sheets contact each other at many joints so that the radiant noise level from the device is low. Examples of a device enclosed by a BOX-shaped metal case are measuring instruments such as an oscilloscope and a personal computer.
However, if it is difficult to wholly enclose a device by a BOX-shaped metal case, noise propagated to the cable is not suppressed, and finally, the radiant noise level from the device becomes high.
For example, an image forming apparatus is equipped with not only electrical parts such as a printed board and a cable but also many parts for an electrophotographic process. It also includes a number of parts such as a cartridge and a fixing device which are changed by the user. A paper feed cassette is also provided as a printing medium supply unit. In this case, enclosing the whole device degrades usability. To partially enclose only the printed board and cable by a metal case, a lot of complex parts are necessary, resulting in an increase in the size and cost of the device.
When the I/O port of an ASIC connects to only another IC in the same printed board, the influence on radiant noise is small because there is no connection to the cable serving as an antenna. In an image forming apparatus, however, the ASIC often has a number of I/O ports which are connected to circuits on other printed boards via cables. This increases the influence on radiant noise.
In patent reference 15, a plurality of power supply terminals provided in one IC are distributed to the main power supply plane and a sub power supply plane which is formed into an island shape and has no bypass capacitor. Power to some terminals is selectively supplied from the power supply planes. This arrangement can reduce the number of bypass capacitors and prevent common-mode noise generated by, e.g., the high-speed switching operation of the IC for leaking to the main power supply plane. According to patent reference 15, a GND plane layer connected to a ground potential is formed so that the internal logic GND terminal of the ASIC connects to a stable GND potential. For this reason, noise leakage from the internal logic GND poses no serious problem.
However, if the IC operation becomes quicker, and its harmonic noise reaches a noise frequency where the impedance of the GND plane is no longer negligible, the current flowing to the GND plane layer formed as a common impedance changes to a noise source. The noise frequency is, e.g., approximately 500 MHz to 5 GHz. This makes the GND potential of the IC unstable in the high-frequency band. The high-frequency noise generated in the GND plane increases the EMI noise level radiated from the circuit board. To reduce the inductance component of the GND plane, a conductive layer (generally, 35-μm thick copper foil) is thickened by several times. However, this increases the cost.
In a single-layered single-sided printed board or a two-layered double-sided printed board, the inductance component of the GND plane is relatively large. For this reason, the wiring impedance of the GND pattern has an effect even in a lower frequency band (e.g., 100 MHz to 200 MHz band). This makes the GND potential of the IC unstable. The high-frequency noise propagated to the GND pattern is propagated to the power supply terminal of the I/O buffer part via the GND terminal of the I/O buffer part and the bypass capacitor. That is, the high-frequency noise is propagated to all input/output signal terminals of the IC.
As described above, in a single-layered single-sided printed board or a two-layered double-sided printed board, it is impossible to form a power supply plane and GND plane capable of supplying a stable power supply voltage and reference GND potential to the entire printed board. As a measure against noise, the GND pattern is connected by a solid GND structure which is as close to a four-layered board as possible. An ASIC mounted on a single-layered single-sided printed board or a two-layered double-sided printed board is rarely a very high speed, large scale integrated circuit, unlike an IC mounted on a four-layered printed board, from the viewpoint of the application purpose. Hence, a measure against noise is taken by making the area of the solid GND as large as possible.
However, even in an ASIC which is mounted on a single-layered single-sided printed board or a two-layered double-sided printed board and operates at a relatively low clock speed (e.g., about 10 MHz to 20 MHz), the packaging density of the internal core circuit is increasing year after year. As a result, the number of switching elements such as CMOS used in the internal core circuit is increasing, and the operation speed is becoming higher.
Even when the system clock speed used for an actual operation is as low as about 20 MHz, the rise speed (Tr) and fall speed (Tf) of a system clock pulse used in an internal operation exhibit a steep signal waveform. This increases the instantaneous carrying current that flows due to switching of the internal core circuit driven by the system clock.
The frequency of the recently used system clock is also becoming higher in inverse proportion to the decrease in the cost of the IC. Since the rise speed (Tr) and fall speed (Tf) of the system clock pulse increase, and the speed of the system clock itself also increases, the frequency band of the harmonic component contained in radiant noise becomes high. When the frequency of the radiant noise component is high, the impedance value by the pattern wiring on the printed board increases, and the GND potential of the printed board becomes increasingly unstable. In the single-layered single-sided printed board or two-layered double-sided printed board incapable of forming a flat power supply wiring line or GND wiring line, unlike the four-layered printed board, the impedance up to a relatively stable frame GND increases so that the influence on the GND terminal potential of the IC increases more and more.
For example, the power supply and GND terminals of the internal core part and those of I/O buffer parts provided in a single IC are arranged almost at the same location in consideration of the size of the entire printed board. For this reason, in the IC having a number of power supply and GND terminals, the wiring impedance between the power supply terminals or GND terminals is smaller than the impedance up to the frame GND, and interference in a high-frequency band occurs more readily than before. That is, the high-frequency potential variation generated in the power supply and GND terminals of the internal core circuit is more easily propagated to those of the I/O buffer unit via the pattern wiring on the printed board. Consequently, the radiant noise level propagated to the signal input/output terminals of the I/O buffer unit becomes high.
In addition, if the single-layered single-sided printed board or two-layered double-sided printed board is changed to a four-layered printed board to form a solid GND with a low impedance, the cost of the printed board largely rises.
The high-frequency potential variation is propagated to the power supply and GND wiring lines on the printed board and all signal input/output lines from the I/O buffer. To prevent this, it is necessary to add a filter onto the printed board or use a ferrite core or shield metal sheet. However, these measures require a very long design time and high cost.